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PD-97174A
RADIATION HARDENED LOGIC LEVEL POWER MOSFET SURFACE MOUNT (SMD-2)
Product Summary
Part Number Radiation Level IRHLNA797064 100K Rads (Si) IRHLNA793064 300K Rads (Si) RDS(on) 0.015 0.015 ID -56A* -56A*
2N7622U2 IRHLNA797064 60V, P-CHANNEL
TECHNOLOGY
SMD-2
International Rectifier's R7TM Logic Level Power MOSFETs provide simple solution to interfacing CMOS and TTL control circuits to power devices in space and other radiation environments. The threshold voltage remains within acceptable operating limits over the full operating temperature and post radiation. This is achieved while maintaining single event gate rupture and single event burnout immunity. These devices are used in applications such as current boost low signal source in PWM, voltage comparator and operational amplifiers.
Features:
n n n n n n n n n n
5V CMOS and TTL Compatible Fast Switching Single Event Effect (SEE) Hardened Low Total Gate Charge Simple Drive Requirements Ease of Paralleling Hermetically Sealed Ceramic Package Surface Mount Light Weight
Absolute Maximum Ratings
Parameter
ID @VGS = -4.5V,TC = 25C ID @VGS = -4.5V,TC = 100C IDM PD @ TC = 25C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current Continuous Drain Current Pulsed Drain Current A Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy A Avalanche Current A Repetitive Avalanche Energy A Peak Diode Recovery dv/dt A Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight * Current is limited by package For footnotes refer to the last page -56* -56* -224 250 2.0 10 1060 -56 25 -3.7 -55 to 150 300 (for 5s) 3.3 (Typical)
Pre-Irradiation
Units
A W
W/C
V mJ A mJ V/ns C g
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1
06/11/07
IRHLNA797064, 2N7622U2
Pre-Irradiation
Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified)
Parameter
BVDSS Drain-to-Source Breakdown Voltage BV DSS /T J Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage VGS(th)/TJ Gate Threshold Voltage Coefficient gfs Forward Transconductance IDSS Zero Gate Voltage Drain Current
Min
-60 -- -- -1.0 -- 82 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- -0.06 -- -- 4.1 -- -- -- -- -- -- -- -- -- -- -- -- 4.0 10520 2780 310 2.3 -- -- 0.015 -2.0 -- -- -1.0 -10 -100 100 190 53 56 38 265 210 70 -- -- -- -- V V/C V mV/C S A nA
Test Conditions
VGS = 0V, ID = -250A Reference to 25C, ID = -1.0mA VGS = -4.5V, ID = -56A A VDS = VGS, ID = -250A VDS = -15V, IDS = -56A A VDS= -48V ,VGS=0V VDS = -48V, VGS = 0V, TJ = 125C VGS = -10V VGS = 10V VGS = -4.5V, ID = -56A VDS = -30V VDD = -30V, ID = -56A, VGS = -6.0V, RG = 2.35
IGSS IGSS Qg Q gs Q gd td(on) tr td(off) tf LS + LD Ciss C oss C rss Rg
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance
nC
ns
nH
pF
Measured from the center of drain pad to center of source pad VGS = 0V, VDS = -25V f = 1.0MHz f = 1.0MHz, open drain
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD t rr Q RR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- -56* -224 -5.0 159 430
Test Conditions
A
V ns nC Tj = 25C, IS = -56A, VGS = 0V A Tj = 25C, IF = -56A, di/dt -100A/s VDD -25V A
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
* Current is limited by package
Thermal Resistance
Parameter
RthJC RthJ-PCB Junction-to-Case Junction-to-PC board
Min Typ Max Units
-- -- -- 1.6 0.5 --
C/W
Test Conditions
soldered to a 2 square copper-cladboard
Note: Corresponding Spice and Saber models are available on International Rectifier Web site. For footnotes refer to the last page
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Radiation Characteristics Pre-Irradiation
IRHLNA797064, 2N7622U2
International Rectifier Radiation Hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance program at International Rectifier is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-3 package. Both pre- and post-irradiation performance are tested and specified using the same drive circuitry and test conditions in order to provide a direct comparison.
Table 1. Electrical Characteristics @ Tj = 25C, Post Total Dose Irradiation AA
Parameter
BVDSS V GS(th) IGSS IGSS IDSS RDS(on) RDS(on) VSD Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source On-State Resistance (TO-3) Static Drain-to-Source On-state Resistance (SMD-2) Diode Forward Voltage Upto 300K Rads (Si)1
Min
-60 -1.0 -- -- -- -- -- --
Max
Units
V nA A V
Test Conditions
VGS = 0V, ID = -250A VGS = VDS , ID = -250A VGS = -10V VGS = 10V VDS = -48V, VGS=0V VGS = -4.5V, ID = -56A VGS = -4.5V, ID = -56A VGS = 0V, ID = -56A
-- -2.0 -100 100 -10 0.015 0.015 -5.0
1. Part numbers IRHLNA797064, IRHLNA793064
International Rectifier radiation hardened MOSFETs have been characterized in heavy ion environment for Single Event Effects (SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2.
Table 2. Single Event Effect Safe Operating Area
Ion LET
(MeV/(mg/cm )) Br I Au 37 60 82
2
Energy Range
(MeV) 305 370 390 (m) 39 34 30
@VGS=
VDS (V)
@VGS= @VGS= @VGS= @VGS= @VGS= @VGS= @VGS=
0V -60 -60 -60
2V -60 -60 -60
4V -60 -60 -60
5V -60 -40 -
6V -40 -20 -
7V -30 -
8V -25 -
10V -20 -
-70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 VGS 6 7 8 9 10
Br I Au
For footnotes refer to the last page
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VDS
Fig a. Single Event Effect, Safe Operating Area
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IRHLNA797064, 2N7622U2
Pre-Irradiation
10000
-I D, Drain-to-Source Current (A)
10000
VGS TOP -10V -7.5V -5.0V -4.5V -3.5V -3.0V -2.5V BOTTOM -2.25V
VGS -10V -7.5V -5.0V -4.5V -3.5V -3.0V -2.5V BOTTOM -2.25V TOP
1000
-I D, Drain-to-Source Current (A)
1000
100 -2.25V 10 60s PULSE WIDTH Tj = 25C 1 0.1 1 10 100 -VDS , Drain-to-Source Voltage (V)
100 -2.25V 10 60s PULSE WIDTH Tj = 150C 1 0.1 1 10 100 -VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
1.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = -56A
-I D, Drain-to-Source Current (A)
T J = 25C T J = 150C
100
1.0
VDS = -25V 15 60s PULSE WIDTH 10 2 2.5 3 3.5 4 -VGS, Gate-to-Source Voltage (V)
VGS = -4.5V
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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Pre-Irradiation
IRHLNA797064, 2N7622U2
RDS(on), Drain-to -Source On Resistance (m )
25 20
ID = -56A
RDS(on), Drain-to -Source On Resistance ( m)
30
18 T J = 150C 16
TJ = 150C 15 10 T J = 25C 5 0 2 4 6 8 10 12
14
12 T J = 25C Vgs = -4.5V 8 0 20 40 60 80 100 -I D, Drain Current (A)
10
-V GS, Gate -to -Source Voltage (V)
Fig 5. Typical On-Resistance Vs Gate Voltage
Fig 6. Typical On-Resistance Vs Drain Current
-V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
75
2.0
70
-VGS(th) Gate threshold Voltage (V)
ID = -1.0mA
1.5
65
1.0
60
0.5
55
ID = -50A ID = -250A
ID = -1.0mA ID = -150mA
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
50 -60 -40 -20 0 20 40 60 80 100 120 140 160
TJ , Temperature ( C )
T J , Temperature ( C )
Fig 7. Typical Drain-to-Source Breakdown Voltage Vs Temperature
Fig 8. Typical Threshold Voltage Vs Temperature
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IRHLNA797064, 2N7622U2
Pre-Irradiation
16000 14000 12000
C oss = C ds + C gd
C, Capacitance (pF)
10000 8000 6000 4000 2000 0 1
Ciss
-VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHz C iss = C gs + C gd, C ds SHORTED C rss = C gd
12 ID = -56A VDS= -48V VDS= -30V VDS= -12V
8
Coss
4
Crss
10 100
FOR TEST CIRCUIT SEE FIGURE 17 0 0 50 100 150 200 250 300 QG, Total Gate Charge (nC)
-VDS, Drain-to-Source Voltage (V)
Fig 9. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 10. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
120
LIMITED BY PACKAGE
-I SD , Reverse Drain Current (A)
-ID , Drain Current (A)
4 5
100
T J = 150C
100
80
T J = 25C 10
60
40
1 VGS = 0V 0.1 0 1 2 3 -V SD , Source-to-Drain Voltage (V)
20
0
25
50
75
100
125
150
TC , Case Temperature (C)
Fig 11. Typical Source-to-Drain Diode Forward Voltage
Fig12. Maximum Drain Current Vs. Case Temperature
6
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Pre-Irradiation
IRHLNA797064, 2N7622U2
1000
EAS , Single Pulse Avalanche Energy (mJ)
-I D, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
2400
100s
2000
100
1600
ID TOP -25A -35.4A BOTTOM -56A
1ms
10
1200
800
10ms
Tc = 25C Tj = 150C Single Pulse 1 10 -V DS , Drain-to-Source Voltage (V) 100
400
1
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Fig 13. Maximum Safe Operating Area
Fig 14. Maximum Avalanche Energy Vs. Drain Current
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20 0.10 0.05 SINGLE PULSE ( THERMAL RESPONSE )
P DM t1 t2
0.01
0.02 0.01
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)
Fig 15. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRHLNA797064, 2N7622U2
Pre-Irradiation
VDS
L
I AS
RG
D.U.T
IAS
+
DRIVER
V DD VDD
A
VGS -20V
tp
0.01
15V
tp V(BR)DSS
Fig 16a. Unclamped Inductive Test Circuit
Fig 16b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
-4.5V
QGS VG
QG QGD
50K
-12V 12V
.2F .3F
VGS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 17a. Basic Gate Charge Waveform
Fig 17b. Gate Charge Test Circuit
V DS VGS RG V GS
Pulse Width 1 s Duty Factor 0.1 %
RD
td(on) tr t d(off) tf
VGS
D.U.T.
+
10%
V DD
90% VDS
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
8
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+
D.U.T.
-
VDS
-
Pre-Irradiation
IRHLNA797064, 2N7622U2
Footnotes:
A Repetitive Rating; Pulse width limited by
maximum junction temperature. A VDD = -25V, starting TJ = 25C, L= 0.67mH Peak IL = -56A, VGS = -10V A ISD -56A, di/dt -380A/s, VDD -60V, TJ 150C
A Pulse width 300 s; Duty Cycle 2% A Total Dose Irradiation with VGS Bias.
-10 volt VGS applied and VDS = 0 during irradiation per MIL-STD-750, method 1019, condition A. A Total Dose Irradiation with VDS Bias. -48 volt VDS applied and VGS = 0 during irradiation per MlL-STD-750, method 1019, condition A.
Case Outline and Dimensions -- SMD-2
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 06/2007
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